1. Field of the Invention
The present invention relates to a semiconductor device suitable for use as a protection circuit for protecting an integrated circuit against electrostatic discharge (ESD), and in particular to improvements for the purposes of enhancing current drivability and accelerating a turn-on operation.
2. Description of the Background Art
Conventionally, ESD protection circuits have been utilized for preventing integrated circuits formed in semiconductor substrates from being damaged by the application of a positive or negative high voltage, as overshooting or undershooting input voltage, due to the accumulation of electrostatic charge in the human body or machinery. Semiconductor controlled rectifiers (generally referred to as xe2x80x9cSCRsxe2x80x9d) are a kind of such ESD protection circuits.
FIGS. 42 and 43 are a cross-sectional view and a circuit diagram of a conventional SCR, respectively. This SCR 200 is formed in an SOI substrate including a supporting substrate 201, a buried insulation film 202, and an SOI (semiconductor on insulator) layer 203 and is utilized as a protection circuit for protecting an internal circuit 212, which is an integrated circuit being protected, against ESD. In the main surface of the SOI layer 203, STI (shallow trench isolation) as a partial isolating layer 204 which does not reach the buried insulation film 202 is selectively formed, by which a plurality of element regions SR100, SR101, and SR102 are partially isolated from each other.
The SOI layer 203 includes a p layer 205 which is adjacent to the buried insulation film 202. In the element region SR100 of the SOI layer 203, an n layer 206 is selectively formed in the main surface, and an n+ layer 207, a p+ layer 208, and an n+ layer 209 are also selectively formed in the main surface to cover the surface of the p layer 205. In the element region SR101, an n+ layer 210 is formed in the main surface. In the element region SR102, a p+ layer 211 is formed in the main surface.
The p+ layer 208, the n layer 206, and the p layer 205 form the collector, base, and emitter of a pnp bipolar transistor NB100, respectively, while the n layer 206, the p layer 205, and the n+ layer 210 form the collector, base, and emitter of an npn bipolar transistor PB100, respectively. Further, the p+ layer 208 forms a resistive element R100 while the n+ layer 210 forms a resistive element R101.
In this fashion, the SCR 200 comprises the two bipolar transistors NB100 and PB100 of different conductivity types, the collector of one transistor being connected to the base of the other transistor and the base of one transistor being connected to the collector of the other transistor. The bipolar transistors NB100 and PB100 thus constitute a positive feedback circuit.
The n+ layer 207 and the p+ layer 208 are connected through a node (a connection in the wiring) N100 to an anode A, and the n+ layer 210 and the p+ layer 211 are connected through a node N101 to a cathode C. The anode A is connected to a wire 213 for use in transmission of an input signal T1 to the internal circuit 212.
FIG. 44 is a graph schematically showing the current-voltage characteristics of the SCR 200. When the anode-cathode voltage (the potential of the anode A relative to the cathode C) VAC rises from 0 in a positive direction, the SCR 200 is kept in a high impedance state where the current I1 hardly flows, until the voltage VAC reaches a switching voltage VS. However, when the voltage VAC exceeds the switching voltage VS, the SCR 200 quickly transits to a low impedance state where a large current flows. The SCR 200 will be kept in this low impedance state until the current I1 flowing through the SCR 200 falls beneath a holding current IH.
Thus, when ESD causes the voltage of the input signal T1 (FIG. 42) to overshoot the source voltage VDD to VDD+xcex94VDD, the anode-cathode voltage VAC of the SCR 200 exceeds the switching voltage VS before the internal circuit 212 is broken and thus the SCR 200 transits from the high impedance state to the low impedance state. Then, current larger than the holding current IH flows through the SCR 200 and the voltage of the input signal T1 decreases before the overshoot voltage VDD+xcex94VDD is transmitted to the internal circuit 212.
A surge voltage caused by ESD is high but its amount of charge is limited; therefore, the current flowing through the SCR 200 will fall beneath the holding voltage IH in due course. As a result, the SCR 200 returns back to its initial or high impedance state from the low impedance state. In this way, the SCR 200 protects the internal circuit 212 against damage from ESD.
U.S. Pat. No. 6,015,992 discloses an SCR which comprises MOSFETs (MOS field-effects transistors) formed in an SOI substrate. FIG. 45 is a perspective view of the SCR disclosed in this U.S. Patent when viewed angularly from the above, and FIG. 46 is a cross-sectional view of this SCR 300 of FIG. 45, taken along the section line Z1-Z2. FIG. 47 is a circuit diagram of the SCR 300 of FIG. 45.
The SCR 300 is also formed in an SOI substrate including a supporting substrate 301, a buried insulation film 302, and an SOI layer 350. In the main surface of the SOI layer 350, STI as a full isolating layer 303 which reaches the buried insulation film 302 is selectively formed, by which a plurality of element regions SR200, SR201, SR202, and SR203 are fully isolated from each other.
In the element region SR200, p+ layers 308, 309 and a p layer 304 are formed. The p layer 304 forms a resistive element R200. In the element region SR203, n+ layers 316, 317 and an n layer 307 are formed. The n layer 307 forms a resistive element 210.
In the element region SR201, a p layer 305, n layers 318, 319, n+ layers 310, 311, and a p+ layer 312 are formed. The n layer 318 and the n+ layer 310 form the source of an n-channel MOSFET, and the n layer 319 and the n+ layer 311 form the drain thereof. In particular, the n layers 318 and 319 make extensions which are parts of the source/drain (herein a pair of source and drain is generically referred to as a xe2x80x9csource/drainxe2x80x9d).
Part of the p layer 305 is opposed to a gate 323 with a gate insulating film 322 therebetween. Further, sidewalls or insulators 324, 325 are formed on the side surfaces of the gate 323. The p layer 305 and the p+ layer 312 form the body of the n-channel MOSFET. Especially, a portion of the p layer 305 of the body which is sandwiched between the source/drain 310, 318, 311 and 319 and is opposed to the gate 323 functions as a channel. Also, the p+ layer 312 of the body where connections with wiring are made is called a body contact region.
The n+ layer 310, the p layer 305 (and the p+ layer 312), and the n+ layer 311 form the emitter, base, and collector of an npn bipolar transistor PB200, respectively. That is, the element region SR201 has formed therein the bipolar transistor PB200 as a parasitic bipolar transistor of the n-channel MOSFET.
The element region SR202 is formed to be symmetrical to the element region SR201 with respect to the conductivity type. More specifically, an n layer 306, p layers 320, 321, p+ layers 313, 314, and an n+ layer 315 are formed in the element region SR202. The p layer 320 and the p+ layer 313 form the drain of a p-channel MOSFET, and the p layer 321 and the p+ layer 314 form the source thereof. In particular, the p layers 320 and 321 make extensions which are parts of the source/drain.
Part of the n layer 306 is opposed to a gate 327 with a gate insulating film 326 therebetween. Further, sidewalls or insulators 328, 329 are formed on the side surfaces of the gate 327. The n layer 306 and the n+ layer 315 form the body of the p-channel MOSFET. Especially, a portion of the n layer 306 of the body which is sandwiched between the source/drain 313, 320, 314, and 320 and is opposed to the gate 327 functions as a channel. Also, the n+ layer 315 of the body where a connection with wiring is made corresponds to a body contact region.
The p+ layer 313, the n layer 306 (and the n+ layer 315), and the p+ layer 314 form the collector, base, and emitter of a pnp bipolar transistor NB200, respectively. That is, the element region SR202 has formed therein the bipolar transistor NB200 as a parasitic bipolar transistor of the p-channel MOSFET.
The base and collector of the bipolar transistor PB200 are individually connected to the collector and base of the bipolar transistor NB200 through the wiring. The bipolar transistors NB200 and PB200 thus constitute a positive feedback circuit. In FIGS. 45 to 47, nodes N201 to N205 represent connections in the wiring.
The emitter and base of the bipolar transistor PB200 are connected with each other through the wiring, and the emitter and base of the bipolar transistor NB200 are also connected with each other through the wiring. This is equivalent to the condition that the p layer 305 as the body of the n-channel MOSFET is fixed to the n+ layer 310 as the source thereof and the n layer 306 as the body of the p-channel MOSFET is fixed to the p+ layer 314 as the source thereof.
Further, the gate 323 is connected through the wiring to the n+ layer 310 as the source, while the gate 327 is connected through the wiring to the p+ layer 314 as the source. One end of the resistive element R200 is connected through the wiring to the anode A, while one end of the resistive element R210 is connected through the wiring to the cathode C.
With such a construction, the SCR 300, like the SCR 200, can be utilized as a protection circuit for protecting an internal circuit against damage from ESD.
Now, the SCR used as a protection circuit is required to have the function of transiting to the low impedance state by being turned on before the voltage of the input signal T1 rises, thereby to absorb the current and change the voltage of the input signal T1 (FIG. 42), which travels through the wiring, back to normal. From this, the SCR should preferably have a high operating speed.
In the SCR 200, however, the current flows laterally (i.e., in a direction along the main surface of the substrate) through the bipolar transistor PB100 formed in the SOI substrate. Therefore, a limitation to the thickness of the SOI layer 203 or the thickness of a portion of the SOI layer 203 directly below the partial isolating layer 204 (i.e., a portion of the SOI layer 203 sandwiched between the partial isolating layer 204 and the buried insulation film 202) causes problems of low current drivability and a delay in turn-on operation.
Similarly in the SCR 300, the current flows laterally through the bipolar transistors PB200 and NB200 formed in the SOI substrate. Thus, the limited thickness of the SOI layer 350 causes problems of low current drivability and a delay in turn-on operation.
An object of the present invention is to provide a semiconductor device capable of enhancing current drivability and accelerating the turn-on operation.
A first aspect of the present invention is directed to a semiconductor device comprising: a semiconductor controlled rectifier having two bipolar transistors of different conductivity types, one of the two bipolar transistors having its base and collector connected respectively to a collector and a base of the other of the two bipolar transistors; and a diode connected inversely in parallel to the collector and emitter of the one bipolar transistor.
According to a second aspect of the present invention, the semiconductor device of the first aspect further comprises two resistive elements, wherein the two bipolar transistors each have its base and emitter connected with each other through one of the two resistive elements.
According to a third aspect of the present invention, in the semiconductor device of the second aspect, the two bipolar transistors, the two resistive elements, and the diode are formed in an SOI layer of an SOI substrate.
According to a fourth aspect of the present invention, in the semiconductor device of the third aspect, a partial isolating layer is selectively formed in a main surface of the SOI layer, and the two resistive elements are formed in portions of the SOI layer sandwiched between the partial isolating layer and a buried insulation film.
According to a fifth aspect of the present invention, the semiconductor device of the fourth aspect further comprises other two resistive elements formed in other portions of the SOI layer sandwiched between the partial isolating layer and the buried insulation film, wherein one of the other two resistive elements is interposed between the base of the other bipolar transistor and a connection between the collector of the one bipolar transistor and one of the two resistive elements, and the other of the other two resistive elements is interposed between the base of the one bipolar transistor and a connection between the collector of the other bipolar transistor and the other of the two resistive elements.
According to a sixth aspect of the present invention, in the semiconductor device of the fifth aspect, impurity concentration is higher in the other portions of the SOI layer than in the portions of the SOI layer so that resistance of the other two resistive elements is lower than that of the two resistive elements.
According to a seventh aspect of the present invention, in the semiconductor device of any of the first to sixth aspects, the two bipolar transistors each have its emitter being one of the source and drain of a MOSFET, its collector being the other of the source and drain of the MOSFET, and its base being the body of the MOSFET.
According to an eighth aspect of the present invention, in the semiconductor device of the seventh aspect, the two MOSFETs each have its gate connected to the source.
According to a ninth aspect of the present invention, in the semiconductor device of the eighth aspect, the two MOSFETs each have a metal-semiconductor compound film which is formed across surfaces of its gate and source to establish a connection between the gate and the source.
According to a tenth aspect of the present invention, in the semiconductor device of the ninth aspect, in each of the two MOSFETs, the metal-semiconductor compound film is also formed across a surface of the body to establish connections for the gate, the source, and the body.
According to a eleventh aspect of the present invention, in the semiconductor device of any of the first to fourth aspects, the two bipolar transistors are formed of semiconductor layers, which are alternately jointed in an p-n-p-n order, to be equivalent in configuration.
According to a twelfth aspect of the present invention, in the semiconductor device of any of the first to eleventh aspects, the diode is a BCG (body coupled gate) diode or a MOSFET whose gate and body are connected to one side of the source and the drain.
According to a thirteenth aspect of the present invention, in the semiconductor device of the twelfth aspect, the BCG diode has a metal-semiconductor compound film which is formed across a surface of the one side and a surface of a portion of the body which is not covered with the gate, to establish a connection between the one side and the body.
According to a fourteenth aspect of the present invention, in the semiconductor device of the thirteenth aspect, in the BCG diode, the metal-semiconductor compound film is also formed across a surface of the gate to establish a connection to the gate.
In accordance with the device of the first aspect, the diode is connected inversely in parallel to the bipolar transistor constituting a semiconductor controlled rectifier. This encourages the positive feedback function of the semiconductor controlled rectifier, thereby enhancing current drivability and accelerating a turn-on operation. The device is thus suitable for use as a protection circuit, which can show high protection capability.
In accordance with the device of the second aspect, the two bipolar transistors each have its base and emitter connected with each other through a resistive element. The base potential can thus be fixed, which stabilizes the operation of the semiconductor controlled rectifier.
In accordance with the device of the third aspect, the two bipolar transistors, the two resistive elements, and the diode are formed in the SOI layer of the SOI substrate. It is thus readily possible to provide full isolation between each element. Although those elements are formed in the SOI layer, the diode, due to its positive-feedback encouraging function, enhances current drivability of the semiconductor controlled rectifier and accelerates the turn-on operation thereof. The device is thus sufficiently suitable for use as a protection circuit.
In accordance with the device of the fourth aspect, the two resistive elements are formed in the portions of the SOI layer between the partial isolating layer and the buried insulation film. Thus, the resistance can be readily set to a moderately high value. This stabilizes the operation of the semiconductor controlled rectifier and accelerates the turn-on operation thereof. Further, it is also readily feasible to adjust the resistance to a desired value by adjusting the widths and lengths of the portions of the SOI layer in which the resistive elements are formed, and impurity concentration therein.
In accordance with the device of the fifth aspect, the presence of other two resistive elements stabilizes the operation of the semiconductor controlled rectifier. Further, it is also readily feasible to set the resistance to a desired value by adjusting the widths and lengths of the portions of the SOI layer in which the other two resistive elements are formed, and impurity concentration therein.
In accordance with the device of the sixth aspect, the resistance of the other two resistive elements are set lower than that of the two resistive elements, which accelerates the turn-on operation of the semiconductor controlled rectifier. Further, the resistance can be readily adjusted by varying impurity concentration.
In accordance with the device of the seventh aspect, the two bipolar transistors are formed as parasitic bipolar transistors of MOSFETs. This facilitates the manufacturing processes and reduces the cost of manufacture.
In accordance with the device of the eighth aspect, the two MOSFETs each have its gate connected to the source. This reduces the holding voltage of the semiconductor controlled rectifier and accelerates the turn-on operation thereof.
In accordance with the device of the ninth aspect, the two MOSFETs each have a metal-semiconductor compound film which establishes a connection between the gate and the source. The gate can thus be short-circuited with the source with low resistance and stability.
In accordance with the device of the tenth aspect, in each of the two MOSFETs, the metal-semiconductor compound film which establishes a connection between the gate and the source also establishes a connection to the body. Thus, the body potential can be fixed to the source potential with low resistance and stability.
In accordance with the device of the eleventh aspect, the two bipolar transistors are equivalently formed of semiconductor layers, which are alternately jointed in an p-n-p-n order. This allows a reduction in device size.
In accordance with the device of the twelfth aspect, the diode is a BCG diode and thus superior in switching characteristics because the ratio of current to voltage variations is high in an ON to OFF or OFF to ON transition. This further encourages the positive feedback function of the semiconductor controlled rectifier.
In accordance with the device of the thirteenth aspect, the BCG diode has a metal-semiconductor compound film which establishes a connection between the body and one side of the source and the drain. The above one side and the body can thus be short-circuited with low resistance and stability. This reduces the resistance of the diode and thus increases the current flowing therethrough, thereby speeding up the switching operation of the semiconductor controlled rectifier.
In accordance with the device of the fourteenth aspect, in the BCG diode, the metal-semiconductor compound film is also connected to the gate. Thus, the above one side, the body, and the gate can be short-circuited with low resistance and stability.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.